When analog video signals such as R′G′B′ (red-green-blue) or Y′PbPr (luma-chroma) video signals of a video graphics source, are processed in a digital video processing circuit, such as employed in a digital television receiver, graphics digitizers that perform analog-to-digital conversion are utilized to convert the analog signals to a digital format. The conversion of a signal including color content from an analog to a digital format generally utilizes three analog-to-digital converters (ADCs), which convert, for example, red, green, and blue analog signals to digital signals simultaneously. In analog-to-digital conversion, identifying the correct sampling frequency for the ADCs is essential since even a small error in sampling frequency can impair the resulting displayed images. The phase of the sampling clock for analog-to-digital conversion is also critical since improper selection of phase can also create undesirable visible effects. The sampling phase is the point in time within a sampling clock's cycle for triggering the ADC. Thus, when a pixelated display device is driven with analog signals, particularly analog signals that originate from a digital source such as a PC (personal computer), a processing arrangement or circuit is required to automatically search for the correct sampling frequency to produce a high quality image. This is necessary because analog signals are generally produced from signals derived from a clock with frequency that is generally not perfectly synchronized with the frequency of a local clock controlling the analog-to-digital converters. In addition, a circuit or process may also be required to automatically search for the appropriate sampling phase, as described in co-pending application Ser. No. 11/187,313, filed Jul. 21, 2005, which is hereby incorporated herein by reference.
Examples of graphics display devices developed for personal computers and television receivers that can utilize a digital video signal are liquid crystal displays (LCDs) and DLP® image projection systems. LCDs offer space savings, lower radiation, and lower power consumption compared to cathode-ray tube (CRT) monitors which can directly use analog video inputs. DLP® image projection arrangements enable implementation of systems displaying a large, high-definition image at reasonable cost. Since an analog display interface is still a widely used interface between an image source and a display device, particularly in the personal-computer industry, the use of graphics digitizers to convert analog signals to digital signals has become a vital process for interfacing image sources to digital display devices such as LCDs. Commercial devices formed as integrated circuits are available to provide analog-to-digital video conversion. Such devices generally contain three ADCs that simultaneously convert red, green, and blue analog video signals to corresponding video signals in a digital format.
FIG. 1 illustrates an exemplary block diagram showing interconnection of signals in a pixelated video system, for example, a “digital display system.” Pixilated video systems are distinguishable from analog display systems such as CRTs by displaying images with fixed pixel locations that are formed in a manufacturing process. CRTs display an image over a continuous surface such as the surface of a CRT, and accordingly, can be driven directly with analog signals.
In the block diagram illustrated in FIG. 1, video or graphics images are generated by a video/graphics card 101 such as a video/graphics card in a personal computer. Digital images are converted in this card to analog waveforms by digital-to-analog converters (DACs) such as DAC 105. Digital signals such as RGB signals in a digital format are supplied to the DAC from an external source (not shown). The analog waveforms produced by the digital-to-analog conversion are coupled over line 135 to digital signal processing device 102 and converted to a digital format by ADC 115. Control circuitry 110 controls the DAC and produces horizontal and vertical synchronization signals HSYNC and VSYNC that are coupled to the display device over line 140. In the display device, a clock generation circuit 130, usually implemented with a phase-locked loop (PLL), generates a sampling clock signal though a phase control circuit 120 to control the sampling instant of the ADC and display circuitry 125. In such display applications, a key issue for high quality image recovery is accurate determination of both the sampling frequency and the sampling phase for the ADCs. These two factors have a dominant impact on the quality of displayed images.
A phase-locked loop 200 such as illustrated in FIG. 2 is commonly used to generate the sampling frequency for the ADCs. When a PLL is locked onto the horizontal synchronization signal (HSYNC), its output can be used as the sampling clock for the ADCs. The dividing ratio of the programmable frequency divider 225 is typically controlled by an input signal, 227, related to the “number of total pixels per video line” for a given video/graphics mode. Thus, the resulting frequency of the sampling clock is the HSYNC frequency multiplied by the “number of total pixels per video line.” Ideally, by this mechanism, the sampling clock will have the same frequency as that of the pixel clock in the video card. However, this does not occur in practice because the low frequency HSYNC signal is usually noisy and has significant timing jitter. Furthermore, its frequency may not be accurate. In addition, the pixel clock frequency of the image source such as a video/graphics card might not be equal to a specified frequency. As a result, the original image that is encoded in the analog signals may not be accurately recovered. Thus, a process to accurately determine the sampling frequency is essential in practical applications to display the high quality images demanded by PC and digital television applications.
In the exemplary block diagram illustrated in FIG. 2, PFD 205 is a frequency and phase detector that converts the frequency or phase difference of its two inputs to voltage signals. The voltage-controlled oscillator (VCO) 220 is an oscillator with frequency dependent on an input control voltage. The programmable frequency divider 225 in the feedback loop divides the VCO frequency to a proportionately lower value dependant on the dividing ratio signal 227. The charge pump 210 and the loop filter 215 convert and filter the PFD output to a signal level with noise sufficiently attenuated that it can be utilized as input by the VCO. The output of the VCO (which is the sampling clock of the ADC) is locked to the HSYNC signal through the programmable frequency divider. The dividing ratio of the programmable frequency divider determines the VCO frequency. Ideally, this ratio should be the number of pixels per video line. However, the number represented by the “number of pixels per video line” is not always consistently used by video sources such as video card vendors, and the resulting frequency will not be correct in those cases, again demonstrating that an improved frequency detection process is required to find the correct dividing ratio so that a high quality image can be displayed.
Eglit, in U.S. Pat. No. 5,847,701 entitled “Method and Apparatus Implemented in a Computer System for Determining the Frequency Used by a Graphics Source for Generating an Analog Display Signal,” dated December, 1998, describes searching sampling frequencies using predetermined test patterns. Sequences of test patterns are encoded in an analog video source and transmitted to a digital display device where the analog signal is converted to sequences of sampled values. The digital display device determines whether the sampled values equal one of the sequences of the test patterns based on a predetermined convention. The digital display device changes the sampling frequency until the sampled values equal one of the test pattern sequences, and the corresponding frequency is used as the ADC sampling frequency when a match is found. Thus, Eglit in U.S. Pat. No. 5,847,701 requires predetermined test patterns encoded in an analog video source, which in turn requires additional hardware and software. Unfortunately, display device designers usually do not have control over how the video source is configured and how it is designed. Moreover, the operation uses a feedback system which does not specify how the next sampling frequency should be determined. The scheme just varies the sampling frequency, which poses a convergence timing problem. Thus, using the method described by Eglit, a mechanism is still required to efficiently determine the next sampling frequency and impractical constraints placed thereby on the display device designer are not resolved.
Nakano, in U.S. Pat. No. 6,097,444 entitled “Automatic Image Quality Adjustment Device Adjusting Phase of Sampling Clock for Analog Video Signal to Digital Video Signal Conversion,” dated August, 2000, describes choosing the sampling frequency by detecting the HSYNC and VSYNC frequencies and comparing them to the commonly used industry standard video timing data. The standard video timing mode whose timing data most closely resembles the detected HSYNC and VSYNC frequencies is the desired mode. The corresponding pixel frequency is used as the sampling frequency. However, a problem with this scheme is that the pixel frequency specified in industry standards is often used just as a guideline. In real applications, significant frequency deviations occur and a degree of frequency error in the pixel clock is unavoidable, the latter of which adversely affects image quality.
West, in U.S. Pat. Nos. 5,805,233 and 5,767,916, both entitled “Method and Apparatus for Automatic Pixel Clock Phase and Frequency Correction in Analog to Digital Video Signal Conversion,” presents a method of determining a pixel clock sampling frequency using the actual width of a video image, measured by the number of pixel clock cycles, and compares it to an expected image width to adjust the pixel clock sampling frequency. However, the methods described by West depend on the absence of blanked regions in the video image to produce an accurate pixel clock sampling frequency.
Other approaches to selecting the correct sampling clock frequency use a static lookup table which involves building a large table that contains all potential clock candidates as well as all the information that is used in the search and identification of the optimum clock candidate. The data in this table would generally include a variety of statistics about the analog video source such as horizontal and vertical synchronization rates, blanking time, active data area, image refresh frequency, etc.
Table approaches to selecting sampling clock frequency can be a burden to a digital system in several ways. One is cost, because an entire table of video image characteristics must be stored within the digital system. A second is the time required to search the table to identify an optimal clock candidate. A third is the need for continuing product support for table updates to accommodate new analog graphics sources that may be developed after product development.
Further approaches utilize the image aspect ratio to compute the sampling clock frequency. Some digital systems calculate the sampling clock frequency by scaling the horizontal pixel resolution by a ratio of the total horizontal system clock time per video line to the active horizontal system clock time per video line. This approach works well when the analog video signal has detectable data across the active portion of the horizontal line and the image is of a known aspect ratio, such as an aspect ratio of 4:3. But in recent years, various “wide-mode” analog graphics sources have appeared. These sources can have various image aspect ratios such as 16:9, 16:10, etc., and sometimes the image aspect ratios are unpredictable. Since there is no way to determine beforehand the image aspect ratio reliably, this method cannot handle the present and expected range of wide-mode analog graphics signals.
In order to correctly adjust the sample clock frequency using the timing ratio described above, useful image data must be present across the active video region. When there is no data at the left or right borders of the image, for example, when the image contains “black borders,” such as the black borders 404 and 405 as shown in FIG. 4, the actual system clock measurement will be incorrect, and the sampling clock frequency will not be calculated correctly. In FIG. 4, a video image 400 is illustrated with an active region including black borders 404 and 405 on the left and right sides, respectively, of a detected active region 406.
The main limitations of the prior art circuits are thus imprecise, unreliable, or impractical determination of the sampling frequency for reconstruction of an image for a digital display device. Prior art approaches use processes that employ test patterns or image data tables, rely on imprecise clocks for digital to-analog conversion, compute with noisy data, rely on the absence of blanked areas on the sides of the image, and depend on signals with substantial overshoot and undershoot. A need thus exists for an apparatus and method to accurately determine the sampling frequency and to select a reliable sampling phase so that a digital image can be displayed that is not degraded by these limitations.